The present invention relates to a semiconductor device and a method of manufacturing the same, in particular, to an effective technology applied to a semiconductor device having redistribution interconnects in a WPP (Wafer Process Package) technology.
The WPP technology (or WLP (Wafer Level Package) technology) is a technology of integrating a wafer process (pre-process) and a package process (post-process) and finishing packaging while in the wafer process. This WPP technology is advantageous because it needs far fewer steps than a technology in which the package process is performed for each of semiconductor chips cut out from a semiconductor wafer. In the package process of the WPP technology, redistribution interconnects electrically coupled to semiconductor elements formed in the pre-process are formed by the plating process and covered with a surface protective film.
Japanese Unexamined Patent Publication No. 9 (1997)-306914 (patent document 1) discloses a technology for forming dummy plating patterns over a semiconductor wafer together with real patterns which become the actual interconnects as a method of forming interconnects for semiconductor elements. This patent document 1 is aimed to form uniform plating interconnects stably as interconnects for semiconductor elements and does not teach the stable formation of redistribution interconnects in the WPP technology.
[Patent document 1]
    Japanese Unexamined Patent Publication No. 9 (1997)-306914